1. Field of the Invention
The present invention relates to a fabrication method for an integrated circuit. More particularly, the present invention relates to a fabrication method for a via.
2. Description of the Related Art
The multilevels interconnect structure has been widely employed to accommodate the escalating demands of high densificiation and performance associated with the design of the continued downscaling of the device dimensions in the ultra large scale integration semiconductor devices. To electrically connect the various levels of different metal layers, the via plug technique has been developed
FIG. 1 is a schematic, cross-sectional view of an interconnect structure according to the prior art. The conventional methodology for forming an interconnect structure involves the formation of a dielectric layer 102, which can either be an interlevel metal dielectric layer (ILD) or an interlevel metal dielectric layer (IMD), on a substrate 100. A metal layer, such as aluminum or an aluminum alloy, is then deposited on the first dielectric layer 102. The metal layer is further patterned to form a metal conductive feature such as a metal conductive line 104. An interlevel metal dielectric layer (IMD), such as spin-on-glass (SOG), is then formed on the resulting metal conductive feature 104. An opening 108 is further formed in the inner metal dielectric layer (IMD). A conductive material is formed filling the opening 108 to form a via plug 110, where the entire bottom surface of the via plug 110 is in a direct contact with the metal conductive feature 104.
Accompanying the increase of the integration of a semiconductor device, the density of the interconnect structures, as shown in FIG. 1, is also greatly increased. As a result, the borderless via technique, which provides a space saving advantage, gradually becomes the core technology for the fabrication of these types of interconnect structures. In a highly integrated device, however, the borderless via plug 110 is often not aligned with the underlying metal conductive feature 104, resulting in an incomplete landing on the metal conductive feature 104 and extending off of the metal conductive feature onto the surrounding dielectric material. This type of misalignment critically affects the yield of the production, and a method to correctly stack the borderless via plug 110 on the metal conductive feature 104 is thereby therefore needed.